The present invention is related to an apparatus for coding data to record coded data on a recording/reproducing apparatus for reproducing and decoding the recorded data. More specifically, the present invention is directed to a method for coding and decoding data.
To understand the present invention, the conventional technique will be briefly explained. The conventional technique involves explanations about the Viterbi algorithm and trellis representation, the partial response channel, and the error correction.
The Viterbi algorithm is to determine a most likelihood path along branches of a trellis diagram. The respective branches of the trellis diagram are weighted with respect to the values of input signals. The Viterbi algorithm may determine such a path for constituting the most likelihood degree based upon the accumulated value of these weighted values.
A so-called xe2x80x9cPRML (Partial Response Maximum Likelihood) systemxe2x80x9d is widely used in magnetic recording/reproducing apparatuses. In this PRML system, the partial response (PR) channel is combined with this Viterbi algorithm. A system polynomial known as the partial response class 4 (PR4) is expressed by G(D)=(1xe2x88x92D)(1+D), assuming now that symbol xe2x80x9cDxe2x80x9d is a delay operator. Furthermore, with respect to high density recording operations, it is known that the extended partial response class 4 (EPR4), the extended EPR4 of G(D)=(1xe2x88x92D)(1+D)3, and the MEEPR4 (Modified Extended EPR4) of G(D)=(1xe2x88x92D2)(5+4D+2D2) are suitably employed. The extended partial response class 4 is expressed by a higher-order of G(D)=(1xe2x88x92D)(1+D)2.
As the system capable of suppressing an occurrence of such an error, and the method for improving the decoding performance, the following idea is conceivable. In this decoding performance improving method, the errors which occur at the same time are locally corrected. That is, as described in the publication entitled xe2x80x9cA New Target Response with Parity Coding for High Density Magnetic Recording Channelsxe2x80x9d written by Thomas Conway (IEEE Transactions on Magnetics, Vol. 34, No. 4, July 1998), the parity bit is added to the code word when the data is recorded, whereas the error detection/correction are carried out when the data is read. For example, the minimum distance decoding error in the extended EPR4ML is the 3-bit continuous error. Such an odd-numbered bit error can be detected during the reproducing operation by adding a 1-bit parity bit thereto.
In the above-described EEPR4ML made by combining the EEPR4 channel with the Viterbi decoding circuit, and MEEPR4ML made by combining the MEEPR4 with the Viterbi decoding circuit, both the Euclid distance between the correct information series and the erroneous information series, and also the error events at this time are express as follows:
EEPR4ML:
(1) error event of distance 6
xc2x1(+xe2x88x92+)
(2) error event of distance 8
xc2x1(+xe2x88x92+xe2x88x92. . . )(length is longer than, or equal to 4)
xc2x1(+xe2x88x92+00+xe2x88x92+)
(3) error event of distance 10
xc2x1(+)
(4) error event of distance 12
xc2x1(+xe2x88x92)
MEEPRML:
(1) error event of distance 48
xc2x1(+xe2x88x92+)
(2) error event of distance 68
xc2x1(+xe2x88x92+xe2x88x92. . . ) (length is longer than, or equal to 4)
(3) error event of distance 70
xc2x1(+)
(4) error event of distance 76
xc2x1(+xe2x88x92+000+xe2x88x92+)
In any case, the minimum distance decoding error is the 3-bit error, and this 3-bit error can be detected by employing such a parity code by which the odd-numbered bit error can be detected. However, as to the more than 4-bit continuous errors corresponding to the subsequent event errors having the short distances, the odd-numbered bit continuous bit errors contained therein cannot be detected. There is another problem that also as to the detectable odd-numbered bit error, the circuit required to specify this bit length during the error correction becomes complex.
As a consequence, an object of the present invention is to reduce an occurrence of such an error event which cannot be detected while an error is corrected.
To solve the above-described problems, a coding method according to the present invention is featured by that while a parity bit capable of detecting an error during reproducing operation is generated, a coding operation is carried out in such a manner that a specific pattern is not contained in a code word series to which this parity bit is added. At the same time, a coding apparatus of the present invention is arranged by that while a most likelihood path is searched based upon the Viterbi algorithm, such a transition path is not selected during the path searching stage. This transition path corresponds to a specific pattern which has been removed from the code word series by the coding operation. As a consequence, for example, if the specific pattern corresponds to xe2x80x9c1111xe2x80x9d, then it is possible to avoid an occurrence of more than 4-bit continuous errors in the decoding errors. Since this coding arrangement is combined with the error detection/correction, the decoding characteristic can be improved.